d a t a sh eet product speci?cation file under integrated circuits, ic06 december 1990 integrated circuits 74hc/hct7080 16-bit even/odd parity generator/checker for a complete data sheet, please also download: the ic06 74hc/hct/hcu/hcmos logic family specifications the ic06 74hc/hct/hcu/hcmos logic package information the ic06 74hc/hct/hcu/hcmos logic package outlines
december 1990 2 philips semiconductors product speci?cation 16-bit even/odd parity generator/checker 74hc/hct7080 features word-length easily expanded by cascading generates either even or odd parity for 16-data bits output capability: standard i cc category: msi general description the 74hc/hct7080 are high-speed si-gate cmos devices. they are specified in compliance with jedec standard no. 7a. the 74hc/hct7080 are 16-bit parity generators or checkers commonly used to detect errors in high-speed data transmission or data retrieval systems. the even and odd parity output is available for generating or checking even/odd parity up to 16-bits. the even/odd parity output (e/ o) is high when an even number of data inputs (i 0 to i 15 ) are high and the cascade/even-odd-changing input ( x) is high. expansion to larger word sizes is accomplished by connecting the even/odd parity output (e/ o) to the cascade/even-odd-changing input ( x) of the final stage. quick reference data gnd = 0 v; t amb =25 c; t r =t f = 6 ns notes 1. c pd is used to determine the dynamic power dissipation (p d in m w): p d =c pd v cc 2 f i + ? (c l v cc 2 f o ) where: f i = input frequency in mhz f o = output frequency in mhz ? (c l v cc 2 f o ) = sum of outputs c l = output load capacitance in pf v cc = supply voltage in v 2. for hc the condition is v i = gnd to v cc for hct the condition is v i = gnd to v cc - 1.5 v ordering information see 74hc/hct/hcu/hcmos logic package information . symbol parameter conditions typical unit hc hct t phl/ t plh propagation delay c l = 15 pf; v cc =5 v i n to e/ o 2932ns x to e/ o 1215ns c i input capacitance 3.5 3.5 pf c pd power dissipation capacitance per package notes 1 and 2 24 25 pf
december 1990 3 philips semiconductors product speci?cation 16-bit even/odd parity generator/checker 74hc/hct7080 pin description pin no. symbol name and function 1 x cascade/even-odd-changing input 2, 3, 4, 5, 6, 7, 8, 9, 11, 12, 13, 14, 15, 16, 17, 18 i 0 to i 15 data inputs 10 gnd ground (0 v) 19 e/ o even/odd parity output 20 v cc positive supply voltage fig.1 pin configuration. fig.2 logic symbol. fig.3 iec logic symbol.
december 1990 4 philips semiconductors product speci?cation 16-bit even/odd parity generator/checker 74hc/hct7080 function table notes 1. h = high voltage level l = low voltage level e = even inputs outputs i n xe/ o ? =e h l h l ?1 eh l l h fig.4 functional diagram. fig.5 logic diagram.
december 1990 5 philips semiconductors product speci?cation 16-bit even/odd parity generator/checker 74hc/hct7080 dc characteristics for 74hc for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: standard i cc category: msi ac characteristics for 74hc gnd = 0 v; t r =t f = 6 ns; c l = 50 pf symbol parameter t amb ( c) unit test conditions 74hc v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. t phl / t plh propagation delay i n to e/ o 91 33 26 280 56 48 350 70 60 420 84 71 ns 2.0 4.5 6.0 fig.7 t phl / t plh propagation delay x to e/ o 41 15 12 150 30 26 190 38 33 225 45 38 ns 2.0 4.5 6.0 fig.6 t thl / t tlh output transition time 19 7 6 75 15 13 95 19 16 110 22 19 ns 2.0 4.5 6.0 figs 6 and 7
december 1990 6 philips semiconductors product speci?cation 16-bit even/odd parity generator/checker 74hc/hct7080 dc characteristics for 74hct for the dc characteristics see 74hc/hct/hcu/hcmos logic family specifications . output capability: standard i cc category: msi note to hct types the value of additional quiescent supply current ( d i cc ) for a unit load of 1 is given in the family specifications. to determine d i cc per input, multiply this value by the unit load coefficient shown in the table below. ac characteristics for 74hct gnd = 0 v; t r =t f = 6 ns; c l = 50 pf input unit load coefficient i n x 1.0 1.0 symbol parameter t amb ( c) unit test conditions 74hct v cc (v) waveforms + 25 - 40 to + 85 - 40 to + 125 min. typ. max. min. max. min. max. t phl / t plh propagation delay i n to e/ o 37 63 79 95 ns 4.5 fig.7 t phl / t plh propagation delay x to e/ o 18 32 40 48 ns 4.5 fig.6 t thl / t tlh output transition time 7 15 19 22 ns 4.5 figs 6 and 7
december 1990 7 philips semiconductors product speci?cation 16-bit even/odd parity generator/checker 74hc/hct7080 ac waveforms fig.6 waveforms showing the cascade/even-odd-changing input ( x) to the even/odd parity output (e/ o) propagation delays and the output transition times. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v. fig.7 waveforms showing the data inputs (i n ) to the even/odd parity output (e/ o) propagation delays and the output transition times. (1) hc : v m = 50%; v i = gnd to v cc . hct: v m = 1.3 v; v i = gnd to 3 v.
december 1990 8 philips semiconductors product speci?cation 16-bit even/odd parity generator/checker 74hc/hct7080 test circuit and waveforms package outlines see 74hc/hct/hcu/hcmos logic package outlines . fig.8 test circuit for measuring ac performance. c l = load capacitance including jig and probe capacitance (see ac characteristics for values). r t = termination resistance should be equal to the output impedance z o of the pulse generator. family amplitude v m t r ; t f f max ; pulse width other 74hc v cc 50% < 2 ns 6 ns 74hct 3.0 v 1.3 v < 2 ns 6 ns fig.9 input pulse definitions. c l = load capacitance including jig and probe capacitance (see ac characteristics for values). r t = termination resistance should be equal to the output impedance z o of the pulse generator. family amplitude v m t r ; t f f max ; pulse width other 74hc v cc 50% < 2 ns 6 ns 74hct 3.0 v 1.3 v < 2 ns 6 ns
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